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Dual, Precision JFET High Speed Operational Amplifier OP249
FEATURES
Fast slew rate: 22 V/s typical Settling time (0.01%): 1.2 s maximum Offset voltage: 300 V maximum High open-loop gain: 1000 V/mV minimum Low total harmonic distortion: 0.002% typical Improved replacement for AD712, LT1057, OP215, TL072, and MC34082
PIN CONFIGURATIONS
OUT A -IN A +IN A V-
1 2 3 4
OP249
A B
8 7 6 5
V+ OUT B
00296-001
00296-002
-IN B +IN B
Figure 1. 8-Lead CERDIP (Q-8) and 8-Lead PDIP (N-8)
+IN A
1 2 3 4 8
-IN A OUT A V+ OUT B
APPLICATIONS
Output amplifier for fast DACs Signal processing Instrumentation amplifiers Fast sample-and-holds Active filters Low distortion audio amplifiers Input buffer for ADCs Servo controllers
V- +IN B -IN B
A
7 6 5
OP249
B
Figure 2. 8-Lead SOIC (R-8)
GENERAL DESCRIPTION
The OP249 is a high speed, precision dual JFET op amp, similar to the popular single op amp, the OP42. The OP249 outperforms available dual amplifiers by providing superior speed with excellent dc performance. Ultrahigh open-loop gain (1 kV/mV minimum), low offset voltage, and superb gain linearity makes the OP249 the industry's first true precision, dual high speed amplifier. With a slew rate of 22 V/s typical and a fast settling time of less than 1.2 s maximum to 0.01%, the OP249 is an ideal choice for high speed bipolar DAC and ADC applications. The excellent dc performance of the OP249 allows the full accuracy of high resolution CMOS DACs to be realized.
0.01
Symmetrical slew rate, even when driving large load, such as, 600 or 200 pF of capacitance and ultralow distortion, make the OP249 ideal for professional audio applications, active filters, high speed integrators, servo systems, and buffer amplifiers. The OP249 provides significant performance upgrades to the TL072, AD712, OP215, MC34082, and LT1057.
870ns
100 90
TA = 25C VS = 15V VO = 10V p-p RL = 10k AV = 1
100 90
00296-003
00296-004
10mV
500ns
0.001 20
5V
1s
100
1k
10k 20k
Figure 3. Fast Settling (0.01%)
Figure 4. Low Distortion, AV = 1, RL = 10 k
Figure 5. Excellent Output Drive, RL = 600
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
00296-005
10 0%
10 0%
OP249 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Pin Configurations ........................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Typical Performance Characteristics ..............................................7 Applications Information .............................................................. 13 Open-Loop Gain Linearity ....................................................... 14 Offset Voltage Adjustment ........................................................ 14 Settling Time............................................................................... 14 DAC Output Amplifier.............................................................. 15 Disscusion on Driving ADCs ................................................... 16 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 19
REVISION HISTORY
5/07--Rev. E to Rev. F Updated Format..................................................................Universal Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Table 3 and Table 4....................................................... 5 Changes to Table 5............................................................................ 6 Changes to Figure 31...................................................................... 11 Changes to Figure 37 and Figure 38............................................. 12 Deleted OP249 SPICE Macro-Model Section ............................ 14 Deleted Figure 18; Renumbered Sequentially ............................ 14 Deleted Table I ................................................................................ 15 Changes to Discussion on Driving ADCs Section..................... 17 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 9/01--Rev. D to Rev. E Edits to Features and Pin Connections ..........................................1 Edits to Electrical Characteristics .............................................. 2, 3 Edits to Absolute Maximum Ratings, Package Type, and Ordering Guide..................................................................................4 Deleted Wafer Test Limits and Dice Characteristics Section ......5 Edits to Typical Performance Characteristics................................8 Edits to Macro-Model Figure........................................................ 15 Edits to Outline Dimensions......................................................... 17
Rev. F | Page 2 of 20
OP249 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = 15 V, TA = 25C, unless otherwise noted. Table 1.
Parameter Offset Voltage Long Term Offset Voltage 1 Offset Stability Input Bias Current Input Offset Current Input Voltage Range 2 Symbol VOS VOS IB IOS IVR Conditions Min OP249A Typ 0.2 1.5 30 6 12.5 11 Common-Mode Rejection Power-Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = 11 V VS = 4.5 V to 18 V VO = 10 V, RL = 2 k RL = 2 k 80 1000 12.0 Short-Circuit Current Limit ISC Output shorted to ground 20 Supply Current Slew Rate Gain Bandwidth Product 3 Settling Time Phase Margin Differential Input Impedance Open-Loop Output Resistance Voltage Noise Voltage Noise Density ISY SR GBW tS M ZIN RO en p-p en No load, VO = 0 V RL = 2 k, CL = 50 pF 10 V step 0.01% 4 0 dB gain -33 5.6 22 4.7 0.9 55 1012||6 35 2 75 26 17 16 0.003 15 -12.5 36 50 7.0 18 3.5 1.2 20 -33 5.6 22 4.7 0.9 55 1012||6 35 2 75 26 17 16 0.003 15 -12.5 90 12 1400 12.5 Max 0.5 0.8 75 25 11 80 31.6 500 12.0 -12.5 36 50 7.0 -12.5 90 12 1200 12.5 Min OP249F Typ 0.2 1.5 30 6 12.5 Max 0.7 1.0 75 25 Unit mV mV V/month pA pA V V V dB V/V V/mV V V V mA mA mA mA V/s MHz s Degrees ||pF V p-p nV/Hz nV/Hz nV/Hz nV/Hz pA/Hz V
VCM = 0 V, TA = 25C VCM = 0 V, TA = 25C
50
18 3.5
1.2
Current Noise Density Voltage Supply Range
1 2 3
in VS
0.1 Hz to 10 Hz fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz fO = 1 kHz 4.5
18
4.5
18
Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent wafer lots at 125C with LTPD of three. Guaranteed by CMR test. Guaranteed by design. 4 Settling time is sample tested.
Rev. F | Page 3 of 20
OP249
VS = 15 V, TA = 25C, unless otherwise noted. Table 2.
Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range 1 Symbol VOS IB IOS IVR Conditions VCM = 0 V, TA = 25C VCM = 0 V TA = 25C 11 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = 11 V VS = 4.5 V to 18 V VO = 10 V; RL = 2 k RL = 2 k 76 500 12.0 Short-Circuit Current Limit ISC Output shorted to ground 20 Supply Current Slew Rate Gain Bandwidth Product 2 Settling Time Phase Margin Differential Input Impedance Open-Loop Output Resistance Voltage Noise Voltage Noise Density ISY SR GBW tS M ZIN RO en p-p en No load; VO = 0 V RL = 2 k, CL = 50 pF 10 V step 0.01% 0 dB gain -33 5.6 22 4.7 0.9 55 1012||6 35 2 75 26 17 16 0.003 15 -12.5 36 50 7.0 -12.0 90 12 1100 12.5 Min OP249G Typ 0.4 40 10 12.5 Max 2.0 75 25 Unit mV pA pA V V V dB V/V V/mV V V V mA mA mA mA V/s MHz s Degree ||pF V p-p nV/Hz nV/Hz nV/Hz nV/Hz pA/Hz V
50
18
1.2
Current Noise Density Voltage Supply Range
1 2
in VS
0.1 Hz to 10 Hz fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz fO = 1 kHz 4.5
18
Guaranteed by CMR test. Guaranteed by design.
Rev. F | Page 4 of 20
OP249
VS = 15 V, -40C TA +85C for F grade and -55C TA +125C for A grade, unless otherwise noted. Table 3.
Parameter Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current 1 Input Offset Current1 Input Voltage Range 2 Symbol VOS TCVOS IB IOS IVR 11 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = 11 V VS = 4.5 V to 18 V RL = 2 k; VO = 10 V RL = 2 k 76 500 12 Supply Current
1 2
Conditions
Min
OP249A Typ Max 0.12 1.0 1 4 0.04 12.5 -12.5 110 5 1400 12.5 -12.5 5.6 5 20 4
Min
OP249F Typ Max 0.5 1.1 2.2 0.3 0.02 12.5 6 4.0 1.2
Unit mV V/C nA nA V V V dB V/V V/mV V V V mA
11 80 50 250 12 7.0 -12.5 5.6 7.0 -12.5 90 7 1200 12.5
100
ISY
No load, VO = 0 V
TA = 85C for F grade; TA = 125C for A grade. Guaranteed by CMR test.
VS = 15 V, -40C TA +85C, unless otherwise noted. Table 4.
Parameter Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current 1 Input Offset Current1 Input Voltage Range 2 Symbol VOS TCVOS IB IOS IVR Conditions Min OP249G Typ 1.0 6 0.5 0.04 12.5 -12.5 95 10 1200 12.5 -12.5 5.6 Max 3.6 25 4.5 1.5 Unit mV V/C nA nA V V V dB V/V V/mV V V V mA
11 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = 11 V VS = 4.5 V to 18 V RL = 2 k; VO = 10 V RL = 2 k 76 250 12.0 Supply Current
1 2
100
ISY
No load, VO = 0 V
7.0
TA = 85C. Guaranteed by CMR test.
Rev. F | Page 5 of 20
OP249 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Supply Voltage Input Voltage 2 Differential Input Voltage2 Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range OP249A (Q) OP249F (Q) OP249G (N, R) Junction Temperature Range OP249A (Q), OP249F (Q) OP249G (N, R) Lead Temperature (Soldering, 60 sec)
1 2
1
Rating 18 V 18 V 36 V Indefinite -65C to +175C -55C to +125C -40C to +85C -40C to +85C -65C to +175C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Resistance
Package Type 8-Lead CERDIP (Q) 8-Lead PDIP (N) 8-Lead SOIC (R)
1
JA1 134 96 150
JC 12 37 41
Unit C/W C/W C/W
Absolute maximum ratings apply to packaged parts, unless otherwise noted. For supply voltages less than 18 V, the absolute maximum input voltage is equal to the supply voltage.
JA is specified for worst-case mounting conditions, that is, JA is specified for device in socket for CERDIP and PDIP packages; JA is specified for device soldered to printed circuit board for SOIC package.
ESD CAUTION
Rev. F | Page 6 of 20
OP249 TYPICAL PERFORMANCE CHARACTERISTICS
120 100 TA = 25C VS = 15V RL = 2k 0 GAIN 45 90 m = 55 20 0 -20 1k 135 180 225 100M 120 TA = 25C VS = 15V
OPEN-LOOP GAIN (dB)
80 60 40
POWER SUPPLY REJECTION (dB)
100
80 +PSRR 60 -PSRR 40
PHASE
PHASE (C)
20
00296-009
10k
100k
1M
10M
00296-006
0 10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Open-Loop Gain, Phase vs. Frequency
65 VS = 15V 10 28
Figure 9. Power Supply Rejection vs. Frequency
60
8
GAIN BANDWIDTH PRODUCT (MHz)
26
VS = 15V RL = 2k CL = 50pF
PHASE MARGIN (C)
SLEW RATE (V/s)
24 -SR 22 +SR
m 55 GBW 50 4 6
20
18
00296-010
-50
-25
0
25
50
75
100
00296-007
45 -75
2 125
16 -75
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 7. Phase Margin, Gain Bandwidth Product vs. Temperature
140 120 100 80 60 40 20 0 100
18
00296-008
Figure 10. Slew Rate vs. Temperature
28
TA = 25C VS = 15V
26
COMMON-MODE REJECTION (dB)
TA = 25C VS = 15V RL = 2k
SLEW RATE (V/s)
24
22
20
16
1k
10k
100k
1M
10M
0
0.2
0.4
0.6
0.8
1.0
FREQUENCY (Hz)
DIFFERENTIAL INPUT VOLTAGE (V)
Figure 8. Common-Mode Rejection vs. Frequency
Figure 11. Slew Rate vs. Differential Input Voltage
Rev. F | Page 7 of 20
00296-011
OP249
35 TA = 25C VS = 15V 30
0.01 TA = 25C VS = 15V VO = 10V p-p RL = 10k AV = 1
SLEW RATE (V/s)
25
NEGATIVE
20
POSITIVE
15
10
00296-012 00296-015
5 0 100 200 300 400 CAPACITIVE LOAD (pF)
500
0.001 20
100
1k
10k
20k
Figure 12. Slew Rate vs. Capacitive Load
10 8 6 TA = 25C VS = 15V AVCL = 1 0.1% 4 2 0 -2 -4 -6 -8 -10 0 200 400 600 800 SETTLING TIME (ns) 0.1%
00296-013
Figure 15. Distortion vs. Frequency
0.01 TA = 25C VS = 15V VO = 10V p-p RL = 2k AV = 1
OUTPUT STEP SIZE (V)
0.01%
0.01%
1000
0.001 20
100
1k
10k
20k
Figure 13. Step Size vs. Settling Time
100 TA = 25C VS = 15V
Figure 16. Distortion vs. Frequency
0.01 TA = 25C VS = 15V VO = 10V p-p RL = 600 AV = 1
VOLTAGE NOISE DENSITY (nV/ Hz)
80
60
40
20
00296-014
0 0 100 FREQUENCY (Hz) 1k
10k
0.001 20
100
1k
10k
20k
Figure 14. Voltage Noise Density vs. Frequency
Figure 17. Distortion vs. Frequency
Rev. F | Page 8 of 20
00296-017
00296-016
OP249
0.1 TA = 25C VS = 15V VO = 10V p-p RL = 10k AV = 1
+1V 500mV 1s
-1V
00296-018
0.01 20
100
1k
10k
20k
BANDWIDTH (0.1Hz TO 10Hz) TA = 25C, VS = 15V
Figure 18. Distortion vs. Frequency
60 0.1 TA = 25C VS = 15V VO = 10V p-p RL = 2k AV = 10 50
CLOSED-LOOP GAIN (dB)
Figure 21. Low Frequency Noise
TA = 25C VS = 15V AVCL = 100
40 30 20 10 0 -10
AVCL = 10 AVCL = 5
AVCL = 1
00296-022
00296-019
0.01 20
-20 1k
10k
100k
1M
10M
00296-021
100M
100
1k
10k
20k
FREQUENCY (Hz)
Figure 19. Distortion vs. Frequency
50
Figure 22. Closed-Loop Gain vs. Frequency
0.1 TA = 25C VS = 15V VO = 10V p-p RL = 600k AV = 10
40
TA = 25C VS = 15V
IMPEDANCE ()
30 AVCL = 1 20
AVCL = 10
10
00296-023
AVCL = 100
00296-020
0.01 20
0 100
1k
10k
100k
1M
10M
100
1k
10k
20k
FREQUENCY (Hz)
Figure 20. Distortion vs. Frequency
Figure 23. Closed-Loop Output Impedance vs. Frequency
Rev. F | Page 9 of 20
OP249
30
20 15
OUTPUT VOLTAGE SWING (V)
25
TA = 25C RL = 2k
OUTPUT VOLTAGE (V p-p)
10 5 0 -5 -10
00296-027
20
15 AD8512 10 OP249
00296-024
5
AD712 0 1k
-15 -20
1M FREQUENCY (Hz)
10M
0
5
10 SUPPLY VOLTAGE (V)
15
20
Figure 24. Output Voltage vs. Frequency
90 80 70 VS = 15V RL = 2k VIN = 100mV p-p
Figure 27. Output Voltage Swing vs. Supply Voltage
6.0 VS = 15V NO LOAD 5.8
OVERSHOOT (%)
60 50 40 30 20
AVCL = 1 NEGATIVE EDGE AVCL = 1 POSITIVE EDGE
SUPPLY CURRENT (mA)
00296-025
5.6
5.4
00296-028
10 0
AVCL = 5 0 100 200 300 400
500
5.2 -75
-50
-25
0
25
50
75
100
125
LOAD CAPACITANCE (pF)
TEMPERATURE (C)
Figure 25. Small Overshoot vs. Load Capacitance
16 14 TA = 25C VS = 15V 5.8 +VOHM = |-VOHM| 10 8 6 4
00296-026
Figure 28. Supply Current vs. Temperature
6.0
MAXIMUM OUTPUT SWING (V)
SUPPLY CURRENT (mA)
12
5.6 TA = +125C 5.4 TA = -55C
TA = +25C
5.2 2 0 100
1k LOAD RESISTANCE ()
10k
5.0 0 5 10 SUPPLY VOLTAGE (V) 15
20
Figure 26. Maximum Output Voltage Swing vs. Load Resistance
Figure 29. Supply Current vs. Supply Voltage
Rev. F | Page 10 of 20
00296-029
OP249
180 160 140 120 UNITS 100 80 60 40
00296-030
10k
TA = 25C VS = 15V 415 x OP249 (830 OP AMPS) INPUT BIAS CURRENT (pA)
VS = 15V VCM = 0V 1k
100
10
00296-033
20 0 -1000 -800 -600 -400 -200
0
200
400
600
800
1000
1 -75
-50
-25
0
25
50
75
100
125
VOS (V)
TEMPERATURE (C)
Figure 30. VOS Distribution (N-8)
Figure 33. Input Bias Current vs. Temperature
300 270 240 210 180 UNITS 150 120 90 60 30 0 0 2 4 6 8 10 12 14 16 18 20 22
00296-031
104
VS = 15V -40C TO +85C (830 OP AMPS)
TA = 25C VS = 15V 103
BIAS CURRENT (pA)
102
101
00296-034
24
100 -15
-10
-5
0
5
10
15
TCVOS (V/C)
COMMON-MODE VOLTAGE (V)
Figure 31. TCVOS Distribution (N-8)
50 VS = 15V 40 40 50
Figure 34. Bias Current vs. Common-Mode Voltage
TA = 25C VS = 15V
30
INPUT BIAS CURRENT (pA)
00296-032
OFFSET VOLTAGE (V)
30
20
20
10
10
00296-035
0
0
1
2
3
4
5
0
0
2
4
6
8
10
TIME AFTER POWER APPLIED (Minutes)
TIME AFTER POWER APPLIED (Minutes)
Figure 32. Offset Voltage Warm-Up Drift
Figure 35. Bias Current Warm-Up Drift
Rev. F | Page 11 of 20
OP249
80 80
SHORT-CIRCUIT OUTPUT CURRENT (mA)
TA = 25C VCM = 0V
VS = 15V SOURCE 60 SINK
INPUT OFFSET CURRENT (pA)
60
40
40
20
00296-036
20
00296-038
0 -75
-50
-25
0
25
50
75
100
125
0 -75
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 36. Input Offset Current vs. Temperature
12000 VS = 15V 10000
Figure 38. Short-Circuit Output Current vs. Junction Temperature
OPEN-LOOP GAIN (V/mV)
8000 RL = 10k 6000 RL = 2k
4000
2000
00296-037
0 -75
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
Figure 37. Open-Loop Gain vs. Temperature
Rev. F | Page 12 of 20
OP249 APPLICATIONS INFORMATION
V+ +IN VOUT
100 90
-IN
10 0%
5V A) OP249
1s
100 90
V-
Figure 39. Simplified Schematic (1/2 OP249)
10 0%
2
00296-039
OP249
+3V
3
1/2
5V
1
1s B) LT1057
5k
+18V
6 8
100 90
OP249
+3V
5 4
1/2
7
00296-040
5k
-18V
10 0%
00296-041
Figure 40. Burn-In Circuit
5V C) AD712
1s
The OP249 represents a reliable JFET amplifier design, featuring an excellent combination of dc precision and high speed. A rugged output stage provides the ability to drive a 600 load and still maintain a clean ac response. The OP249 features a large signal response that is more linear and symmetric than previously available JFET input amplifiers. Figure 41 compares the large signal response of the OP249 to other industry-standard dual JFET amplifiers. Typically, the slewing performance of the JFET amplifier is specified as a number of V/s. There is no discussion on the quality, that is, linearity and symmetry of the slewing response.
Figure 41. Large-Signal Transient Response, AV = 1, VIN = 20 V p-p, ZL = 2 k//200 pF, VS = 15 V
The OP249 was carefully designed to provide symmetrically matched slew characteristics in both the negative and positive directions, even when driving a large output load. The slewing limitation of the amplifier determines the maximum frequency at which a sinusoidal output can be obtained without significant distortion. However, it is important to note that the nonsymmetric slewing typical of previously available JFET amplifiers adds a higher series of harmonic energy content to the resulting response--and an additional dc output component. Examples of potential problems of nonsymmetric slewing behavior can be in audio amplifier applications, where a natural low distortion sound quality is desired and in servo or signal processing systems where a net dc offset cannot be tolerated. The linear and symmetric slewing feature of the OP249 makes it an ideal choice for applications that exceed the full power bandwidth range of the amplifier.
Rev. F | Page 13 of 20
OP249
R4 +V
100 90
VIN R1 200k
R3
OP249
R2 31
1/2
VOUT
R5 50k
-V
Figure 44. Offset Adjustment for Inverting Amplifier Configuration
10 0%
00296-042
+V R5 R3 50k R1 200k R2 33 -V VIN R4
50mV
1s
OP249
VOS ADJUST RANGE = V GAIN = VOUT VIN =1+
1/2
VOUT
Figure 42. Small-Signal Transient Response, AV = 1, ZL = 2 k||100 pF, No Compensation, VS = 15 V
As with most JFET input amplifiers, the output of the OP249 can undergo phase inversion if either input exceeds the specified input voltage range. Phase inversion does not damage the amplifier, nor does it cause an internal latch-up condition. Supply decoupling should be used to overcome inductance and resistance associated with supply lines to the amplifier. A 0.1 F and a 10 F capacitor should be placed between each supply pin and ground.
R2 R1
R5 R4 + R2
00296-045
R5 IF R2 << R4 =1+ R4
Figure 45. Offset Adjustment for Noninverting Amplifier Configuration
OPEN-LOOP GAIN LINEARITY
The OP249 has both an extremely high open-loop gain of 1 kV/mV minimum and constant gain linearity, which enhances its dc precision and provides superb accuracy in high closed-loop gain applications. Figure 43 illustrates the typical open-loop gain linearity--high gain accuracy is assured, even when driving a 600 load.
In Figure 44, the offset adjustment is made by supplying a small voltage at the noninverting input of the amplifier. Resistors R1 and R2 attenuate the potentiometer voltage, providing a 2.5 mV (with VS = 15 V) adjustment range, referred to the input. Figure 45 shows the offset adjustment for the noninverting amplifier configuration, also providing a 2.5 mV adjustment range. As shown in the equations in Figure 45, if R4 is not much greater than R2, a resulting closed-loop gain error must be accounted for.
SETTLING TIME
The settling time is the time between when the input signal begins to change and when the output permanently enters a prescribed error band. The error bands on the output are 5 mV and 0.5 mV, respectively, for 0.1% and 0.01% accuracy. Figure 46 shows the settling time of the OP249, which is typically 870 ns. Moreover, problems in settling response, such as thermal tails and long-term ringing, are nonexistent.
870ns 100 90
OFFSET VOLTAGE ADJUSTMENT
The inherent low offset voltage of the OP249 makes offset adjustments unnecessary in most applications. However, where a lower offset error is required, balancing can be performed with simple external circuitry, as shown in Figure 44 and Figure 45.
VERTICAL 50V/DIV INPUT VARIATION
10
00296-043
0% 10mV 500ns
00296-046
HORIZONTAL 5V/DIV OUTPUT CHARGE
Figure 43. Open-Loop Gain Linearity; Variation in Open-Loop Gain Results in Errors in High Closed-Loop Gain Circuits; RL = 600 , VS = 15 V
Figure 46. Settling Characteristics of the OP249 to 0.01%
Rev. F | Page 14 of 20
00296-044
VOS ADJUST RANGE = V
R2 R1
OP249
DAC OUTPUT AMPLIFIER
Unity-gain stability, a low offset voltage of 300 V typical, and a fast settling time of 870 ns to 0.01%, makes the OP249 an ideal amplifier for fast DACs. For CMOS DAC applications, the low offset voltage of the OP249 results in excellent linearity performance. CMOS DACs, such as the PM7545, typically have a code-dependent output resistance variation between 11 k and 33 k. The change in output resistance, in conjunction with the 11 k feedback resistor, results in a noise gain change, which causes variations in the offset error, increasing linearity errors. The OP249 features low offset voltage error, minimizing this effect and maintaining 12-bit linearity performance over the full-scale range of the converter.
VDD 0.1F
18 20
Because the DAC output capacitance appears at the inputs of the op amp, it is essential that the amplifier be adequately compensated. Compensation increases the phase margin and ensures an optimal overall settling response. The required lead compensation is achieved with Capacitor C in Figure 48.
75 C 33pF
2
+15V
VDD REFERENCE OR VIN
19 VREF
RFB OUT1 1
0.1F
8
500
PM7545
AGND 2
3
OP249
4
1/2
1
VOUT
0.1F
00296-047
DB11 TO DB0 DGND 12 DATA INPUT
3
-15V
Figure 47. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance--Unipolar Operation
R4 20k 1% VDD 0.1F 75 C +15V 33pF 0.1F
2 8
R5 10k 1%
18
20
VDD REFERENCE OR VIN
19
RFB OUT1 1
500
VREF
PM7545
AGND 2
3
OP249
1/2
1
R3 10k 1%
5
DB11 TO DB0 12 DATA INPUT
DGND
3
OP249
6 4
1/2
7
VOUT
00296-048
0.1F
-15V
Figure 48. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance--Bipolar Operation
Rev. F | Page 15 of 20
OP249
A 4s 100 90 100 90 B 4s
10 0% 500mV 1s C = 5pF RESPONSE IS GROSSLY UNDERDAMPED, AND EXHIBITS RINGING
10 0% 500mV 1s
00296-049
C = 15pF FAST RISE TIME CHARACTERISTICS, BUT AT EXPENSE OF SLIGHT PEAKING IN RESPONSE
Figure 49. Effect of Altering Compensation from Circuit in Figure 47--PM7545 CMOS DAC with 1/2 OP249, Unipolar Operation; Critically Damped Response Is Obtained with C 33 pF
Figure 49 illustrates the effect of altering the compensation on the output response of the circuit in Figure 47. Compensation is required to address the combined effect of the output capacitance of the DAC, the input capacitance of the op amp, and any stray capacitance. Slight adjustments to the compensation capacitor may be required to optimize settling response for any given application. The settling time of the combination of the current output DAC and the op amp can be approximated by
t S TOTAL =
Figure 50 shows a settling measurement circuit for evaluating recovery from an output current transient. An output disturbing current generator provides the transient change in output load current of 1 mA.
+15V
0.1F
3
8
OP249
2 4
1/2
1
7A13 PLUG-IN
(t S DAC )2 + (t S AMP )2
0.1F * 7A13 PLUG-IN 1k IOUT = |VREF | 1k
The actual overall settling time is affected by the noise gain of the amplifier, the applied compensation, and the equivalent input capacitance at the input of the amplifier.
-15V 300pF +15V 1.5k TTL INPUT 1N4148 +15V 1.8k 220 0.1F * 0.01F 0.47F 2N2907 1k 2N3904 10F
+
DISSCUSION ON DRIVING ADCs
Settling characteristics of op amps also include the ability of the amplifier to recover, that is, settle, from a transient current output load condition. An example of this includes an op amp driving the input from a SAR-type ADC. Although the comparison point of the converter is usually diode clamped, the input swing of plus-and-minus a diode drop still gives rise to a significant modulation of input current. If the closed-loop output impedance is low enough and bandwidth of the amplifier is sufficiently large, the output settles before the converter makes a comparison decision, which prevents linearity errors or missing codes.
*DECOUPLE CLOSE TOGETHER ON GROUND PLANE WITH SHORT LEAD LENGTHS.
Figure 50. Transient Output Impedance Test Fixture
Rev. F | Page 16 of 20
00296-050
VREF
OP249
As seen in Figure 51, the OP249 has an extremely fast recovery of 247 ns (to 0.01%) for a 1 mA load transient. The performance makes it an ideal amplifier for data acquisition systems. The combination of high speed and excellent dc performance of the OP249 makes it an ideal amplifier for 12-bit data acquisition systems. Examining the circuit in Figure 53, one amplifier in the OP249 provides a stable -5 V reference voltage for the VREF input of the ADC912. The other amplifier in the OP249 performs high speed buffering of the input of the ADC. By examining the worst-case transient voltage error at the AIN node of the ADC, it is shown that the OP249 recovers in less than 100 ns (see Figure 52). The fast recovery is due to both the wide bandwidth and low dc output impedance of the OP249.
247.4ns 100 90 5mV 100 90
10 0% 100ns
00296-052
Figure 52. Worst-Case Transient Voltage at Analog In Occurs at the Half-Scale Point of the ADC; the OP249 Buffers the ADC Input from Figure 53 and Recovers in <100 ns
10 0% 2mV 2V 100ns
00296-051
Figure 51. Transient Recovery Time of the OP249 from a 1 mA Load Transient to 0.01%
+15V 0.1F ANALOG INPUT
8
+5V 10F||0.1F
-15V 10F||0.1F
3
OP249
2 4
1/2
1
24
23
0.1F
RD 20
ADC912A
+15V 0.1F -15V
1
AIN
2
CLK IN 17 VREFIN AGND DGND
3 12 19
BUSY 22 HBEN CS
21
2
0.1F
VIN
REF02
VOUT 6 GND
4 6 5
OP249
1/2
1
10 -5V 10F||0.1F
00296-053
Figure 53. OP249 Dual Amplifiers Provide Both Stable -5 V Reference Input and Buffers Input to ADC912A
Rev. F | Page 17 of 20
OP249 OUTLINE DIMENSIONS
0.400 (10.16) 0.365 (9.27) 0.355 (9.02)
8 1 5
4
0.280 (7.11) 0.250 (6.35) 0.240 (6.10)
0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14)
0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
0.015 (0.38) MIN SEATING PLANE 0.005 (0.13) MIN
0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX
0.014 (0.36) 0.010 (0.25) 0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 54. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters)
5.00 (0.1968) 4.80 (0.1890)
4.00 (0.1574) 3.80 (0.1497)
8 1
5 4
6.20 (0.2441) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 55. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
Rev. F | Page 18 of 20
012407-A
070606-A
OP249
0.005 (0.13) MIN
8
0.055 (1.40) MAX
5
0.310 (7.87) 0.220 (5.59)
1 4
0.100 (2.54) BSC 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 15 0 0.015 (0.38) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 56. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model OP249AZ OP249FZ OP249GP OP249GPZ 1 OP249GS OP249GS-REEL OP249GS-REEL7 OP249GSZ1 OP249GSZ-REEL1 OP249GSZ-REEL71
1
Temperature Range -55C to +125C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead CERDIP 8-Lead CERDIP 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N
Package Option Q-8 Q-8 N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8
Z = RoHS Compliant Part.
For Military processed devices, see the standard microcircuit drawings (SMD) available at www.dscc.dla.mil/programs/milspec/default.asp.
Table 7.
SMD Part Number 5962-9151901M2A 5962-9151901MPA Analog Devices, Inc. Equivalent OP249ARCMDA OP249AZMDA
Rev. F | Page 19 of 20
OP249 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00296-0-5/07(F)
Rev. F | Page 20 of 20

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